PowerPC e500
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The PowerPC e500 is a 32-bit Power Architecture based microprocessor core from Freescale. The core is compatible with the older PowerPC Book E specification as well as the current Power ISA v.2.03. It has a dual issue, seven stage pipeline with FPUs, 32/32 KiB data and instruction L1 caches and 256 or 512 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi core operation and interface for auxiliary application processing units (APU).
e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, MPC85xx.
There are two versions of the e500 core, namely e500v1 and the newer e500v2. Key improvements in the e500v2 include:
- increase from 32-bit (4GiB) to 36-bit (64GiB) physical address space
- addition of 1GiB and 4GiB variable-page sizes
- addition of double precision floating point support
- doubling in size and associativity of the MMU's second-level 4K-page array (from 256-entry 2-way to 512-entry 4-way)
- increase from 3 to 5 maximum outstanding data cache misses
- addition of the Alternate Time Base for cycle-granularity timestamps
[edit] e500-mc
Freescale will in 2008 introduce a multi core plattform based on the e500 core and PowerISA v.2.06 which includes hypervisor and virtualisation functionality for embedded plattforms. The new e500-mc core will support anything from 2 to more than 32 cores (not necessarily the same type of cores) on a a single chip, connected with a new communications fabric called FlexNet. The cores will have separate L2 cache, but will share other facilities like multiple L3 cache, RAM, multiple application specific acceleration cores, I/O and such.
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