POWER2
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The IBM POWER2 microprocessor was released in 1993 as the successor of the POWER1. The POWER2 ran from 55 to 71.5 MHz and improved on the POWER1 design by featuring an extra fixed point unit and floating point unit, increased cache sizes and new instructions. The POWER2, like the POWER1 was a multichip design, requiring eight dies with a total transistor count of 23 million transistors and a total die area of 1215 mm² manufactured in a 0.72 µm five layer metal process and was packaged in a ceramic multi-chip module. Performance for a 62.5 MHz model was 73.3 SPECint92 and 134.6 SPECfp92 according to IBM.
The P2SC (POWER2 Super Chip) was released in 1996 as the successor of the POWER2. A single chip implementation of the POWER2's eight chip design, the P2SC contained 15 million transistors on a 335 mm² die manufactured in IBM's 0.29 µm five layer metal CMOS-6S process and ran at 135 MHz, nearly twice as fast as the POWER2 at 71.5 MHz, with the memory and I/O buses running at half speed to support the higher clock frequency. The P2SC was not a complete copy of the POWER2, the L1 Data Cache and Data TLB capacities were halved to 128 KiB and 256 entries respectively and a rarely used feature that locked entries in the TLB was not implemented in order to fit the original design onto a single die. The P2SC's performance was 5.5 SPECint95_base and 14.5 SPECfp95_base according to IBM. The P2SC was the microprocessor that powered the 30-node IBM Deep Blue supercomputer that beat world champion Garry Kasparov at chess in 1997. In 1998, the P2SC was succeeded by the POWER3 as IBM's flagship microprocessor on the RS/6000 line.
[edit] References
- POWER2: Next Generation of the RS/6000 Family. IBM.
- IBM Crams POWER2 onto Single Chip, by Linley Gwennap. The Microprocessor Report, Volume 10, Number 11, August 26, 1996.