PowerPC e200
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The PowerPC e200 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale for primary use in automotive and industrial control systems. The cores are designed to form the CPU part in system-on-a-chip (SoC) designs with speed ranging up to 600 MHz, thus making them ideal for embedded applications.
The e200 core is developed from the MPC5xx family processors, which in turn is derived from the MPC8xx core in the PowerQUICC SoC processors. e200 adheres to the Power ISA v.2.03 as well as the previous Book E specification. All e200 core based microprocessors are named in the MPC55xx scheme, not to be confused with the MPC52xx processors which is based on the PowerPC e300 core.
In April 2007 Freescale and IPextreme opened up the e200 cores for licensing to other manufacturers.[1]
Continental AG and Freescale are developing SPACE, a tri-core e200 based processor designed for electronic brake systems in cars.[2]
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[edit] Cores
The e200 family consists of four cores, from simple low-end to complex high-end in nature.
[edit] e200z0
The simplest core, e200z0 features an in order, four stage pipeline with no MMU or FPU. It uses the variable bit length (VLE) part of the Power ISA, which uses 16-bit versions of the otherwise standard 32-bit PowerPC Book E ISA, thus reducing code footprint by up to 30%. It has a single 32-bit AMBA bus interface.
The e200z0 is used in the MPC5510 as an optional co-processor alongside an e200z1 core, making that chip a multicore processor.
[edit] e200z1
The e200z1 has a four stage, single-issue pipeline with a branch prediction unit and an 8 entry MMU, but no FPU. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 32-bit AMBA bus interface.
[edit] e200z3
The e200z3 has a four stage, single-issue pipeline with a branch prediction unit, a 16 entry MMU and a SIMD capable FPU. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit AMBA bus interface.
[edit] e200z6
The e200z6 has a seven stage, single-issue pipeline with a branch prediction unit, a 32 entry MMU, a SIMD capable FPU and a 32 KiB unified data/instruction L1 cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit bus AMBA interface.
[edit] Future
At the Power Architecture Developer Conference in 2007 Freescale revealed the roadmap for e200. No timeframe was disclosed nor any real details about the new cores.
- z6 (130 nm) → z6+(90 nm) → z7 (65 and 45 nm)
- z0, z1, z3 (130 nm) → z0h, z4, z4h (90 nm) → z7 (65 and 45 nm)
[edit] See also
[edit] References
- Freescale's MPC55xx page
- IPextremes e200 licensing page
- Freescale’s e200 Core Family, Overview and Licensing Model, White paper
- Multi-Core Design: Key Challenges and Opportunities – Power.org
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