PWRficient

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Power Architecture CPU architecture This box: view • talk • edit
Historical
POWER • PPC6xx • PowerPC-AS • POWER2 • POWER3 • G4 • POWER4 • Gekko • AIM alliance
Current
PowerPC • e200 • e300 • e500 • e600 • PA6T • POWER5 • POWER6 • PPC4xx • PPC750 • PPC970 • CBEA • Xenon • Broadway
Future
POWER7 • e700 • Titan
Related Links
RISC • System p • System i • Power.org • PAPR • PReP • CHRP • more...

PWRficient is the name of a series of microprocessors designed by P.A. Semi.

PWRficient processors comply with the 64-bit Power Architecture, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

The PA6T is the first processor core from P.A. Semi, and it is offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differ in their L2 cache size, their memory controllers, their communication functionality, and their cryptography offloading features. In the future P.A. Semi plans to offer parts with up to 16 cores.

The PA6T core is the first Power Architecture core to be designed from scratch outside the AIM alliance (i.e. not designed by either IBM, Motorola/Freescale, or Apple Computer) in ten years. Since Texas Instruments is one of the investors in P.A. Semi, it is suggested that their fabrication plants will be used to manufacture the PWRficient processors.^[1]

PWRficient processors were initially shipped to select customers in February 2007 and were released for worldwide sale in Q4 2007.^[2]

Contents 1 Implementation 1.1 CPU 1.2 Memory system 1.3 I/O 2 Notable uses 3 Links 4 References

[edit] Implementation

PWRficient processors comprise three parts:

[edit] CPU

PA6T

• Superscalar, out-of-order 32/64 bit Power Architecture processor core.
• Adheres to the Power ISA v.2.04
• Little/big endian operation
• 64/64 KiB instruction and data L1 caches. 32 GB/s bandwidth.
• 6 execution units including a double precision FPU and Altivec unit.
• Hypervisor and Virtualization support.
• max 7W at 2 GHz
• 11 million transistors, 10 mm² large @ 65 nm.

[edit] Memory system

CONEXIUM

• scalable cross-bar interconnect
• 1-8 SMP cores
• 1-2 L2 caches, 512 KiB - 8 MiB large. 16 GB/s bandwidth.
• 1-4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
• 64 GB/s peak bandwidth.
• MOESI coherency

[edit] I/O

ENVOI

• Centralized DMA engine, 32 GB/s bandwidth
• 16-64 SerDes lanes
• XAUI
• PCI Express
• SGMII
• Offload engine for cryptography, RAID, TCP

[edit] Notable uses

• Amiga, Inc. will use the 1682M processor in its new Amiga systems. [1][2]
• Curtiss-Wright will use the 1682M processor in its signal processing systems. [3]
• Mercury Computer Systems will use the 1682M processor in its signal and image processing systems. [4]
• NEC will use the 1682M processor in its storage array systems. [5]

[edit] Links

• P.A. Semi homepage
• Start-up plans new energy-efficient processor
• PA Semi attacks performance/Watt

[edit] References

1. ^ PA Semi heads to 16 cores on back of $50m boost. The Register. Retrieved on 2006-10-17.
2. ^ Press release. P.A. Semi. Retrieved on 2007-02-07.

• FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies
• Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design