IBM z10 (microprocessor)
From Wikipedia, the free encyclopedia
| IBM mainframe | Architecture |
| 700/7000 series | varied |
| System/360 | |
| System/370 | System/370 |
| S/370-XA | |
| ESA/370 | |
| System/390 | ESA/390 |
| zSeries | z/Architecture |
| System z9 | |
| System z10 | |
The z10 is a microprocessor chip made by IBM for their System z10 mainframe computers, released February 26, 2008[1]. It was called "z6" during development[2].
Contents |
[edit] Description
The processor supports the CISC z/Architecture and has four cores, each with 64 kB (64 KiB) instruction and 128 kB data L1 caches, 3 MB (3 MiB) L2 cache and accelerators for cryptography, data compression and decimal floating point arithmetic.
The chip measures 21.7×20.0 mm and will consist of 991 million transistors manufactured with IBMs 65 nm SOI fabrication process (CMOS 11S), supporting speeds of 4.4 GHz and above – more than twice the clock speed as former mainframes – with a 15 FO4 cycle.
Each z10 chip has two 48 GB/s (48 billion bytes per second) SMP hub ports, four 13 GB/s memory ports, two 17 GB/s I/O ports, and 8765 interconnects (pins).
The z10 processor was co-developed with and shares many design traits with the POWER6 processor, such as fabrication technology, logic design, execution unit, floating-point units, bus technology and pipeline design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline.
The processors are quite unlike in other respects, such as cache hierarchy and coherency, SMP topology and protocol, and chip organization. The different ISAs result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a rich CISC architecture backwards compatible all the way back to the IBM System/360 architecture from the 1960s.
Additions to the z/Architecture from the previous z9 EC processor include:
- 50+ new instructions for improved code efficiency
- software/hardware cache optimizations
- support for 1 MB page frames
- decimal floating point fully implemented in hardware.
Error detection and recovery is emphasized, with error-correcting code (ECC) on L2 and L3 caches and buffers, and extensive parity checking elsewhere; in all over 20,000 error checkers on the chip. Processor state is buffered in a way that allows precise core retry for almost all hardware errors.
[edit] Storage Control
Even though the z10 processor has on-die facilities for symmetric multiprocessing (SMP), there is a dedicated companion chip called the SMP Hub Chip or Storage Control (SC) that adds 24 MB off-die L3 cache and lets it communicate with other z10 processors and Hub Chips at 48 GB/s. The Hub Chip consists of 1.6 billion transistors and measures 20.8×21.4 mm, with 7984 interconnects. The design allows each processor to share cache across two Hub Chips, for a potential total of 48 MB of shared L3 cache.
[edit] Multi-chip Module
The z10 chips and the Storage Control chips are mounted on multi-chip modules (MCMs). Each z10 system can have up to 4 MCMs. One MCM consists of five z10 chips and two SC chips, totaling in seven chips per MCM. Due to redundancy and other operating features, not all cores are available to the customer. In the System z10 models E12, E26, E40 and E56 the MCMs have 17 available cores (one, two, three and four MCMs respectively), and the model E64 have one MCM with 17 cores, and three with 20 cores.
[edit] See also
[edit] References
- Redbook Draft: IBM System z10 Enterprise Class Technical Introduction
- IBM System z10 Enterprise Class – Datasheet
- IBM z6 The Next-Generation Mainframe Microprocessor – IBM.com
- IBM Readies Quad-Core z6 Chip for Mainframe Iron – IT Jungle
