32 nanometer
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| CMOS manufacturing processes |
The 32 nanometer (32 nm) process (also called 32 nanometer node) is the next step after the 45 nanometer process in CMOS manufacturing and fabrication. "32 nm" refers to the expected average half-pitch of a memory cell at this technology level. The two major chip rivals, Intel and AMD, are both working on a 32 nanometer process for logic, which uses significantly looser design rules.[citation needed] AMD has partnered with IBM on this process, as it did with the 45 nm process. The 32 nm process is due to arrive in the 2009-2010 timeframe.
[edit] Technology demos
IMEC (Belgium) has recently demonstrated a 32 nm Flash patterning capability based on double patterning and immersion lithography. The introduction of double patterning may offset some of the cost advantages of moving from one node to the next, but may be unavoidable in order to reduce memory cell area.
TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 square micrometer six-transistor SRAM cell in 2005.
IBM demonstrated a 0.143 square micrometer SRAM cell, produced using electron-beam lithography and optical lithography on the same layer. It was observed that the static noise margin (sensitivity to input voltage fluctuations) degraded significantly in going to such a small SRAM cell size. The poly gate pitch was 135 nm.
Intel showed the first 32nm test chips to the public on September 18, 2007 at the Intel Developer Forum. At the release, several technical details were disclosed. A second-generation high-k gate dielectric and metal gate were used. The cell size was 0.182 square micrometers and the chip contained almost 2 billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers.
Not to be outdone, in late October 2007, Samsung disclosed a 30 nm NAND Flash patterning process, using self-aligned double patterning. Starting from a 60 nm half-pitch pattern, new material was deposited and etched in between features to produce a 30 nm half-pitch pattern. Presumably, this can be repeated once more for 15 nm half-pitch.
A common theme for all these demos is the use of double patterning, specifically, the use of two separate exposures to define a critical layer pattern.
As of 2008, the use of double patterning appears inevitable, due to the lack of availability of alternative lithography techniques which meet manufacturing targets (such as throughput).
The successors to 32 nm technology will be 22 nm, and then 16 nm technology per ITRS.
[edit] References
- D. M. Fried et al., IEDM 2004.
- S. Steen et al., Microelec. Eng., vol. 83, pp. 754-761 (2006).
- H-Y. Chen et al., Symp. on VLSI Tech. 2005.
[edit] External links
- Chipmakers gear up for manufacturing hurdles
- Sony, IBM, and Toshiba partnering on semiconductor research
- IBM and AMD partnering on semiconductor research
- Slashdot discussion
- Intel press release
- Intel 32 nm process
- Intel 32 nm SRAM demonstration at IDF 2007
- Samsung press release for 30 nm 64Gb NAND flash
- Samsung self-aligned double patterning technology
| Preceded by 45 nm |
CMOS manufacturing processes | Succeeded by 22 nm |
