中斷
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In computing, an interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution via a context switch, and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven.
An act of interrupting is referred to as an interrupt request ("IRQ").
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[编辑] 概觀
在輪詢（Polling）時，為了避免處理器浪費寶貴的時間等待外部事件發生，因此採用一種叫做硬體中斷的方式。
中斷可由硬體的控制線來當作一套分別的系統實作，或是也可以整合到記憶體系統下。
如果在硬體下實作，在裝置與處理器的中斷接腳之間通常會有一個中斷控制器（controller）電路，用來多工處理數個中斷源，通常對應到一至兩條的處理器線路上。
如果實作成記憶體控制器的一部分，中斷則會對應到系統記憶體位置空間上。 中斷可以分類成：可遮罩式（maskable）中斷（參閱IRQ）、不可遮罩式（non-maskable）中斷（參閱NMI）、內部處理器中斷（interprocessor interrupt，簡稱IPI）、軟體中斷，和偽中斷。
- 可遮罩式中斷（IRQ）是一種硬體中斷，透過設定中斷遮罩暫存器（interrupt mask register; IMR）內的位元遮罩（bit-mask）值來讓它可被系統忽略。
- 同樣地，不可遮罩式（NMI）也是硬體中斷，但卻和位元遮罩無關，意謂著它是無法被系統忽略的。NMI通常使用於計時器（timers），特別像是看門狗計時器（watchdog timers）。
- 內部處理器中斷是一種中斷的特殊案例，在多處理器系統下，由某顆處理器產出中斷來通知另一顆處理器之用。
- 軟體中斷是處理器內執行了某個指令後，所產生出的中斷。軟體中斷通常用來實作成系統呼叫（System calls），因為它們是實作成某種例行性的副程式呼叫，用於處理器保護層級（Ring (電腦安全)）更動時。
- 偽中斷是一種非需求的硬體中斷。在某些系統狀況下會容易發生，如中斷線路上的電子干擾，或是不正確的硬體設計。
處理器通常含有一個內部的中斷遮罩，當這個設定後，可讓軟體忽略所有的外部硬體中斷。在可程式化中斷控制器（PIC）中，相較於去讀取中斷遮罩暫存器（IMR），這個遮罩可提供較快的硬體存取，或是關閉裝置本身的中斷。在某些例子中，像是x86架構下，在處理器本身關閉和開啟中斷會以記憶屏障（memory barrier）的方式運作，在此情況下實際上反而變慢。
若一個中斷使機器處於明確定義的狀態，則稱這中斷為精確中斷（precise interrupt）。這類的中斷有下列四種特性：
- 程式計數器（Program Counter; PC）會存入已知的位置。
- 在PC導向前所有的指令都會執行完畢。
- 超出PC導向後的指令不可以被執行。（並沒有限制超出PC後不可有指令，只是任何對暫存器或記憶體造成的改變必須在中斷發生前復原。）
- PC導向的指令執行狀態是已知的。
任何一種中斷其不符合這些需求的，稱作非精確中斷（imprecise interrupt）。
若耗費過多時間處理中斷，會造成整體系統效能被嚴重阻礙的現象，有人稱作中斷風暴（interrupt storm）。
[编辑] 中斷的種類
[编辑] Level-triggered
A level-triggered interrupt is a class of interrupts where the presence of an unserviced interrupt is indicated by a high level (1), or low level (0), of the interrupt request line. A device wishing to signal an interrupt drives the line to its active level, and then holds it at that level until serviced. It ceases asserting the line when the CPU commands it to or otherwise handles the condition that caused it to signal the interrupt.
Typically, the processor samples the interrupt input at predefined times during each bus cycle such as state T2 for the Z80 microprocessor. If the interrupt isn't active when the processor samples it, the CPU doesn't see it. One possible use for this type of interrupt is to minimize spurious signals from a noisy interrupt line: a spurious pulse will often be so short that it is not noticed.
Multiple devices may share a level-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to its inactive state. Devices actively assert the line to indicate an outstanding interrupt, but let the line float (do not actively drive it) when not signalling an interrupt. The line is then in its asserted state when any (one or more than one) of the sharing devices is signalling an outstanding interrupt.
This class of interrupts is favored by some because of a convenient behavior when the line is shared. Upon detecting assertion of the interrupt line, the CPU must search through the devices sharing it until one requiring service is detected. After servicing this device, the CPU may recheck the interrupt line status to determine whether any other devices also need service. If the line is now deserted, the CPU avoids checking the remaining devices on the line. Since some devices interrupt more frequently than others, and other device interrupts are particularly expensive, a careful ordering of device checks is employed to increase efficiency.
There are also serious problems with sharing level-triggered interrupts. As long as any device on the line has an outstanding request for service the line remains asserted, so it is not possible to detect a change in the status of any other device. Deferring servicing a low-priority device is not an option, because this would prevent detection of service requests from higher-priority devices. If there is a device on the line that the CPU does not know how to service, then any interrupt from that device permanently blocks all interrupts from the other devices.
The original PCI standard mandated shareable level-triggered interrupts. The rationale for this was the efficiency gain discussed above. (Newer versions of PCI allow, and PCI Express requires, the use of message-signalled interrupts.)
[编辑] Edge-triggered
An edge-triggered interrupt is a class of interrupts that are signalled by a level transition on the interrupt line, either a falling edge (1 to 0) or a rising edge (0 to 1). A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its quiescent state. If the pulse is too short to be detected by polled I/O then special hardware may be required to detect the edge.
Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to one particular state. Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signalling an interrupt. This type of connection is also referred to as open collector. The line then carries all the pulses generated by all the devices. However, interrupt pulses from different devices may merge if they occur close in time. To avoid losing interrupts the CPU must trigger on the trailing edge of the pulse (e.g., the rising edge if the line is pulled up and driven low). After detecting an interrupt the CPU must check all the devices for service requirements.
Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, and interrupts will continue to be received from the high-priority devices that are being serviced. If there is a device that the CPU does not know how to service, it may cause a spurious interrupt, or even periodic spurious interrupts, but it does not interfere with the interrupt signalling of the other devices. However, it is fairly easy for an edge triggered interrupt to be missed - for example if interrupts have to be masked for a period - and unless there is some type of hardware latch that records the event it is impossible to recover. Such problems caused many "lockups" in early computer hardware because the processor didn't know it was expected to do something. More modern hardware often has one or more interrupt status registers that latch the interrupt requests; well written edge-driven interrupt software often checks such registers to ensure events are not missed.
The elderly ISA bus uses edge-triggered interrupts, but does not mandate that devices be able to share them. The parallel port also uses edge-triggered interrupts. Many older devices assume that they have exclusive use of their interrupt line, making it electrically unsafe to share them. However, ISA motherboards include pull-up resistors on the IRQ lines, so well-behaved devices share ISA interrupts just fine.
[编辑] Hybrid
Some systems use a hybrid of level-triggered and edge-triggered signalling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time.
A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because NMIs generally signal major \u2013 or even catastrophic \u2013 system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system.
[编辑] Message-signalled
A message-signalled interrupt does not use a physical interrupt line. Instead, a device signals its request for service by sending a short message over some communications medium, typically a computer bus. The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory write.
Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition. Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signalled interrupts with the same message (the same virtual interrupt line) are allowed to merge, just as closely-spaced edge-triggered interrupts can merge.
Message-signalled interrupt vectors can be shared, to the extent that the underlying communication medium can be shared. No additional effort is required.
Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled. This reduces the need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any additional lines.
PCI Express, a serial computer bus, uses message-signalled interrupts exclusively.
[编辑] 共用中斷線路的難度
Multiple devices sharing an interrupt line (of any triggering style) all act as spurious interrupt sources with respect to each other. With many devices on one line the workload in servicing interrupts grows as the square of the number of devices. It is therefore preferred to spread devices evenly across the available interrupt lines. Shortage of interrupt lines is a problem in older system designs where the interrupt lines are distinct physical conductors. Message-signalled interrupts, where the interrupt line is virtual, are favoured in new system architectures (such as PCI Express) and relieve this problem to a considerable extent.
Some devices with a badly-designed programming interface provide no way to determine whether they have requested service. They may lock up or otherwise misbehave if serviced when they do not want it. Such devices cannot tolerate spurious interrupts, and so also cannot tolerate sharing an interrupt line. ISA cards, due to often cheap design and construction, are notorious for this problem. Such devices are becoming much rarer, as hardware logic becomes cheaper and new system architectures mandate shareable interrupts.
[编辑] 特殊用途
Typical interrupt uses include the following: system timers, disks I/O, power-off signals, and traps. Other interrupts exist to transfer data bytes using UARTs or Ethernet; sense key-presses; control motors; or anything else the equipment must do.
A classic system timer interrupt interrupts periodically from a counter or the power-line. The interrupt handler counts the interrupts to keep time. The timer interrupt may also be used by the OS's task scheduler to reschedule the priorities of running processes. Counters are popular, but some older computers used the power line frequency instead, because power companies in most Western countries control the power-line frequency with a very accurate atomic clock.
A disk interrupt signals the completion of a data transfer from or to the disk peripheral. A process waiting to read or write a file starts up again.
A power-off interrupt predicts or requests a loss of power. It allows the computer equipment to perform an orderly shutdown.
Interrupts are also used in typeahead features for buffering events like keystrokes.
[编辑] 延伸閱讀
- Advanced Programmable Interrupt Controller
- Programmable Interrupt Controller
- Inter-processor interrupt
- Interrupt handler
- Interrupt latency
- Non-maskable interrupt
- BIOS interrupt call
[编辑] 外部連結
- A real down to earth explanation of interrupts and interrupt-controllers
- Interrupts Made Easy
- Tutorials about Handling PCI and Parallel Port Interrupts
[编辑] 參閱
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