Simucad
From Wikipedia, the free encyclopedia
| Simucad Design Automation, Inc. | |
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| Type | Private Company |
| Founded | 2004 |
| Headquarters |  Santa Clara, California |
| Key people | Dr Ivan Pesic, President/CEO |
| Industry | Software & Programming |
| Website | www.simucad.com |
Simucad is a provider of circuit simulation and CAD software tools used in the design of analog, mixed-signal, and RF integrated circuits. The company was incorporated in Delaware in June 2004 as a spin-off from Silvaco Data Systems.[1] Simucad acquired ownership all of Silvaco's simulation and CAD products and intellectual property, most notably the SmartSpice circuit simulator.
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[edit] Corporate
Simucad's headquarters are in Santa Clara, California. There are three other direct sales offices in North Chelmsford, MA, Austin, TX, Phoenix, AZ. International sales and distribution is handled through Silvaco's existing network of offices in Japan, Korea, Taiwan, China, Singapore, the UK, Germany, and France.
[edit] Products
The company supplies integrated EDA software in the areas of Analog/Mixed-Signal/RF, Custom IC CAD, Interconnect Modeling, and Digital CAD.
[edit] Analog/Mixed-Signal/RF
UTMOST III - SPICE Modeling Software. Generates SPICE models for analog, digital, mixed-signal, and RF applications. Used to perform data acquisition, device characterization, parameter extraction, and model verification.
UTMOST IV - Optimization Module. Provides a database-driven environment for the generation of SPICE models and macro-models for analog, mixed-signal and RF applications.
SPAYN - Statistical Parameter and Yield Analysis. Statistical modeling tool for analyzing variances from model parameter extraction sequences, electrical test routines, and circuit test measurements. Helps to identify the relationship between device or circuit performance variations and the underlying specific process fluctuations. SPAYN generates worst-case or “process corner” parameter sets and SPICE models reflecting variations in process parameters.
Gateway - Schematic Editor. Front-end of Simucad's Analog/Mixed Signal/RF IC Design Platform. Integrated with Simucad’s circuit simulation, layout, DRC/LVS/LPE, and parasitic extraction tools. Hierarchical editing features are available on Unix, Linux, and Windows.
SmartSpice - Analog Circuit Simulator. Used to design complex analog circuits, analyze critical nets, characterize cell libraries, and verify analog mixed-signal designs. Compatible with popular analog design flows and foundry-supplied device models.
SmartSpiceRF - Harmonic Balance Based RF Simulator. Provides a set of steady-state large-signal analyses and measurements to design GHz range RF ICs driven with multi-tone sources. Simulates harmonic distortion, intermodulation products, gains, noise, oscillator’s phase noise in non-linear circuits using SPICE netlists.
Harmony - Analog/Mixed-Signal Simulator. Simulates circuitry expressed in Verilog, SPICE, Verilog-A and Verilog-AMS. Dynamically links in the capabilities of the SmartSpice Circuit Simulator and SILOS Verilog Simulator at run time.
Verilog-A - Language for SmartSpice. Compiled or interpreted Verilog-A language combined with SmartSpice provides designers with an environment for the design and verification of complex analog and mixed-signal circuits. It provides an executable specification for design integrity and optimization capabilities for achieving those specifications.
[edit] Custom IC CAD
EXPERT - Layout Editor. Offers layout viewing, editing features, and scripting for automation with parameterized cells (PCells).
Guardian - DRC/LVS/LPE Physical Verification products. Provide interactive and batch mode verification of analog, mixed signal and RF IC designs. Integrated with Simucad schematic capture and layout editor. Perform design rule checks (DRC), layout vs. schematic (LVS) comparisons, and layout parameter extractions (LPE).
HIPEX - Full-Chip Parasitic Extraction Products. Perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology. Integrated with the Expert Layout Editor for the complete design flow of DRC/LVS/LPE and RC parasitic extraction on one platform.
[edit] Interconnect Modeling
EXACT - Interconnect Parasitic Characterization. Delivers interconnect models for nanometer semiconductor processes and generates layout parameter extraction (LPE) rule files for leading full chip extraction tools. Includes 3D field solvers that support Mentor xCalibre and Calibre xRC, Cadence DIVA and Dracula LPE, and Simucad HIPEX Full Chip Parasitic Extraction products.
QUEST - High Frequency Parasitic Extractor. Calculates 3D frequency-dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis. Creates frequency-dependent W-element transmission line and spiral inductor standard SPICE models directly from GDSII layouts using an interactive GUI interface. Technology files can be imported or generated within the tool.
CLEVER - Physics-Based Parasitic Extractor. Uses 3D field solvers to directly convert the mask data of a cell and relevant process information into a SPICE netlist, back annotated with the most accurate interconnect capacitance and resistance parasitics. This process removes inaccuracies resulting from traditional, rule-based parasitic extractors.
STELLAR - Core Parasitic Extractor. Fills the circuit size gap between typical small cell solvers and full chip extractors. Uses a field solver algorithm to characterize cells containing up to 50,000 active elements. Transforms mask and process data into a fully back annotated SPICE netlist.
[edit] Digital CAD
SILOS-X - Verilog Simulator. IEEE-1364-2001 compliant simulator used by IC designers. Offers interactive debugging features in a design environment for FPGA, PLD, ASIC, and custom digital designs.
HyperFault - Mixed-Level Fault Simulator. Verilog IEEE-1364-2001 compliant fault simulator that analyses test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing. Uses algorithms to enable efficient multi-pass fault simulation over distributed CPUs.
AccuCell - Characterization and Modeling Tool. Characterizes and validates standard cell libraries, I/Os, and custom cells. Runs SmartSpice to generate the accurate timing and power models required by leading synthesis, simulation, optimization, and analysis tools.
AccuCore - Transistor and Gate Level Full-Chip STA with Automatic Block Characterization. Provides Static Timing Analysis (STA) of complex designs with mixed design styles. Gives designers the ability to characterize a transistor design with SmartSpice accuracy and perform block or full-chip static timing analysis.
[edit] Process Design Kits (PDKs)
Simucad offers process design kits (PDKs) for analog, mixed-signal and RF design teams. These are collections of verified data files that are used by a set of custom IC design EDA tools to provide a design flow. Such data files include schematic symbols, parameterized cells (PCells), DRC/LVS runsets, parasitic extraction runsets, and scripts to automate the generation and verification of design data.
Foundry process-specific models, symbols, and rule decks are integrated and tested with Simucad custom IC design tools and p-cells to create an AMS/RF design environment.
