OpenRISC
From Wikipedia, the free encyclopedia
OpenRISC is an open source hardware RISC CPU design by OpenCores released under the GNU Lesser General Public License. The OpenCores team implemented the design in the verilog hardware description language. Flextronics International and Jennic Ltd. manufactured the OpenRISC as part of an ASIC. Others implemented OpenRISC in a FPGA.
The OpenCores team also ported the GNU toolchain to OpenRISC to support development in several languages. Linux and µClinux have been ported to the processor.
[edit] See also
[edit] External links
- OpenRISC 1200 at the Open Cores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems provides hardware and software solutions for OpenRISC.
- Dynalith Systems provides ICE for OpenRISC, which connects GDB server to Debug Unit through JTAG and is based on USB 2.0.
- IMPERAS MULTI-CORE SOFTWARE DEVELOPMENT TOOLS, MP development and debug tools for virtual platforms running at 100s of MIPS for ARM, MIPS, Tensilica, OpenRISC, and proprietary processors.
- Open Virtual Platforms' OVPsim 500 mips OR1K emulator, enables you to develop software on your PC using virtual platforms, emulators including OpenCores processors running at up to 500 MIPS for OR1K processors running many OSes including ucLinux. OVP is used to build emulators of single OR1K processors or multiple - homogeneous MP or heterogenous MP. See: www.OVPworld.org
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