Talk:Motorola 68060

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Hong Kong To-do:

edit purge

Clean up all MTR station pages. They are literally all over the place. Two model pages are Tsing Yi Station and Sheung Shui Station. They each describe a feature special to the station, Station layout, exit, and connections, as well as neighbouring stations and the station "box".
- We will also need plenty of updated pictures (e.g. removing all KCR-related images except those on the KCR article). Check that all pages have basically the same language structure as Tsing Yi Station and Sheung Shui Station. Links to location maps are good too. (Should also perform these checks on Chinese Wikipedia.)

Clean-up pages that link with TVB, especially its series pages.

Since Freescale does not, and as far as I can figure never did, produce an mc68060, I'm changing the mod that gives them credit for it.

--User:kjs3

I don't understand ... http://www.freescale.com/webapp/sps/site/taxonomy.jsp?nodeId=0162468rH3YTLC61654622 shows that FSL is selling the 040, the 060, etc. Motorola does not sell those devices any more, and while they were developed in the era when SPS was a part of Motorola, it is no longer a Motorola property. Neier 05:14, 1 February 2006 (UTC)

The pentium FPU was definitly pipelined, this was the core of some of the programming tricks used in Quake and is the reason why games based on the quake engine are a lot slower on 68060. --Qdr 22:44, 15 Jul 2004 (UTC)

Random links from google: [1] [2]

I'm going to differ there and so are Intel. Please revert this page to remove the factual inaccuracy. P5's FPU was a low-latency single issue design very much like 68060 and K6. It was not what we'd recognise today as a pipelined design, Intel simply did not have the transistor budget to do that. You can read more on this link. The significant FP advantage of the PentiumPro (P6) came from the pipelined dual-issue FPU design. Quake's performance came from it being coded with Pentium FPU latencies in mind.

I know the Ars technica article. It is very inaccurate, especially when it comes to the Pentium I. But even then it does not even state anything about the Pentium I FPU not being pipelined. How about checking out the actual Intel manuals? Intel Architecture Optimizations Manual

For reference, FPU latency (ADD,MUL) and throughput for the cpus you mentioned:

68060: 3/3 - P5: 3/1 - K6: 2/2

(Wayne replies) I have read your link, and it clearly supports me that P5 did not have a pipelined FPU. Like every other source, like Intel's documentation, like the very people who designed the processor. P5's FPU is not pipelined, it is a single issue design. Any layman examining the processor can see this.

You linked something to support you, but it supports me instead. I think I and established authorities in the field are right here.

Sorry, you are starting to get obnoxious. I quote page 5-2 of the referenced document: Pentium, Pentium Pro and Pentium II processors have a pipelined floating-point unit. By scheduling the floating-point instructions maximum throughput from the Pentium processor floating-point unit can be achieved. --Qdr 14:57, 13 Nov 2004 (UTC)

A thought just crossed my mind: Maybe you are mixing up "pipelining" and "dual issue"? --Qdr 15:59, 13 Nov 2004 (UTC)

[edit] Motorola 68070 merged here

Its AFD debate agreed to do so; I redirected the article here to preserve its page history. Johnleemk | Talk 10:46, 11 December 2005 (UTC)

There was no Motorola 68070 - but there *was* a 68070 - it was used in the CD-i, made by Philips, and I believe it was a clone of the 68000, so it's a bit misleading to redirect 68070 to here. Mdwh 19:17, 18 December 2005 (UTC)

The AFD debate had nothing to do with 68070 being a redirect - feel free to turn it into a disambiguation page. Johnleemk | Talk 19:18, 18 December 2005 (UTC)