Micro-operation
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In computer central processing units, micro-operations, also known as a micro-ops or μops, are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).
Various forms of μops has since long been the basis for traditional microcode routines used to simplify the implementation of a particular CPU design or perhaps just the sequencing of certain multi-step operations or addressing modes. More recently, μops have also been employed in a different way in order to let modern "CISC" processors more easily handle asyncronous parallel and speculative execution: As with traditional microcode, one or more table lookups (or equivalent) is done to locate the appropriate μop-sequence based on the encoding and semantics of the machine instruction (the decoding or translation step), however, instead of having rigid μop-sequences controlling the CPU directly from a microcode-ROM, sequences are here dynamically issued (i.e. buffered) before being used.
This dynamic method means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or "hard-wired") design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction level parallelism out of a normal single-threaded program possible (provided that dependecies are checked etc). The buffering also opens up for certain analysis and reordering of code sequences "on the fly" in order to dynamically optimize mapping and sheduling of μops onto machine resources (such as ALUs, load/store units etc). This often means intermixed sequences of sub-operations (μops) generated for different machine instructions (forming partially reordered machine instructions).
Today, the optimization has gone even further; processors not only translate many machine instructions into a series of μops, but also do the opposite when appropriate; they combine certain machine instruction sequences (such as a compare followed by a conditional jump) into a more complex μop which fits the execution model better and thus can be executed faster or with less machine resources involved.
To further improve performance, some processors (Pentium 4) cache the decoded micro-operations, so that if the same macroinstruction is executed again, the processor can directly access the decoded micro-operations from cache, instead of decoding the macroinstruction again. The Execution Trace Cache found in Intel's NetBurst Microarchitecture is example of this. The size of this cache is often stated in terms of how many thousands of micro-operations it can store, or kμops.
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