IEEE P1801
From Wikipedia, the free encyclopedia
As of November 2007, the IEEE Standards Association DASC sponsored working group IEEE P1801 is working on extending the capabilities of the draft standard contributed by Accellera and extended by the committee to:
- clarify the semantics of the intent - this provides portability of design intent across many vendors tools
- Add support for incremental refinement - Platinum source (constraints) from IP vendors, Golden source (configuration) from IP integrators, and Silicon source (implementation choices) from those that realize the instantiations.
- Add support for bottom up and top down design
- add documentation of the support for wildcard and regular expression selection of design instances
- clarify the differences between ports and pins
- provide for convergence capability from both the Accellera UPF and Si2 Low Power Coalition Common Power Format
The standard includes constructs for describing:
- Power Domains
- Power supplies
- switches
- isolation logic between power domains
- level shifters between power domains
- retention strategies for saving the state of a system during power reduction cycles
- collections of objects to which the constructs may apply
[edit] References
- Download Accellera Unified Power Format draft [UPF specification].
- http://eda.org/p1801 is the workgroup's web page.
