Talk:Complex instruction set computer
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Is the date ("1994-10-10") at the bottom of the page really necessary? It is the date from the FOLDOC entry that this article is based on, I think. I don't see why it is still relevant. I'm going to remove it, but if it's serving some sort of good purpose, go ahead and put it back. James Foster 09:57, 24 Nov 2004 (UTC)
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[edit] References?
"For example, on one processor it was discovered that it was possible to improve performance by not using the procedure call instruction but using a sequence of simpler instructions instead."
Exactly what processor is the author refering to? Or did he just make that up? REFERENCES!!!
- The processor was probably the VAX, and the call instruction was probably either CALLG or CALLS. I remember this being discussed ages ago in the early days of modern RISC. Unfortunately, I don't have a reference right now - either it's not available to Google or it's buried in the welter of pages that match a search for "vax performance callg calls jsr" - but I suspect a reference can be found. I'll keep looking (or you, or somebody else, might find it). Guy Harris 07:08, 1 February 2006 (UTC)
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- I found a similar example with the VAX-11/780 index instruction being slower than an equivalent, simpler instruction sequence. See: http://www.pattosoft.com.au/jason/Articles/HistoryOfComputers/1970s.html (third to last paragraph). This is also mentioned in the book "Computer Organization & Design" by Patterson and Hennessy, 1st Edition (page 350). If you can't find the reference for your original example, perhaps you can use this and link to the webpage I mentioned. Rogerbrent 18:40, 1 February 2006 (UTC)
[edit] CDC 6600 a CISC machine?
This article gives it as an example of a CISC processor, but the CDC 6600 page says "The basis for the 6600 CPU is what we would today refer to as a RISC system, one in which the processor is tuned to do instructions which are comparatively simple and have limited and well defined access to memory." It did, as I remember, have fixed-length instructions, only simple addressing modes, and a load/store architecture, which sounds more RISCy than CISCy; how does it qualify as a CISC processor? Guy Harris 19:33, 19 February 2006 (UTC)
No. It does not qualify as a CISC processor. I removed the reference.--Wws 18:08, 30 October 2006 (UTC)
[edit] Goals and Differences
The nature of RISC is not only that it uses simple instructions but that it keeps the chip simple. CISC makes no effort to simplify the chip-- going for speed and capability and only using simplicity when it’s faster.
[edit] RICH
In the development of architectures, the term RICH meant Rich Instruction CHip, implying individual machine instructions were potentially extremely powerful, sometimes competing with compiler instructions. In the 1980s, CISC supplanted RICH in the trade press, although I consider RICH a more descriptive (and mroe clever) acronym than CISC.
--UnicornTapestry (talk) 23:53, 6 December 2007 (UTC)
- This deserves mention within the CISC article, although I don't believe RICH deserves a separate article.
- [citation needed] Guy Harris (talk) 00:19, 7 December 2007 (UTC)
