DEC 7000/10000 AXP
From Wikipedia, the free encyclopedia
The DEC 7000 AXP and DEC 10000 AXP are a series of high-end multiprocessor server computers developed and manufactured by Digital Equipment Corporation, introduced on 10 November, 1992 (although the DEC 10000 AXP was not available until the following year). These systems formed part of the first generation of systems based on the 64-bit Alpha AXP architecture and at the time of introduction, ran Digital's OpenVMS AXP or OSF/1 AXP operating systems. They were designed in parallel with the VAX 7000 and 10000 minicomputers, and are identical except for the processor module(s) and supported bus interfaces. A field upgrade from a VAX 7000/10000 to a DEC 7000/10000 AXP was possible by means of swapping the processor boards.
The DEC 7000/10000 AXP were intended to supersede the VAX 6000 series, and themselves were succeeded in 1995 by the AlphaServer 8200 (TurboLaser) enterprise server.
Contents |
[edit] Models
The DEC 10000 AXP was essentially a larger configuration of the DEC 7000 AXP. Both shared the same System Cabinet, but the 10000 was configured as standard with one Expander Cabinet housing storage devices, and one Battery Cabinet housing a uninterruptible power supply. These were optional for a DEC 7000 AXP system.
There are two models of the DEC 7000 AXP:
- Model 6x0, code named Laser/Ruby: 182 MHz DECchip 21064 (EV4) processor(s), later available with 200 MHz 21064s (Laser/Ruby+).
- Model 7x0, code named Laser/Ruby45: 275 MHz DECchip 21064A (EV45) processor(s). This model was introduced on November 3, 1994.
There was one model of the DEC 10000 AXP:
- Model 6x0, code named Blazer/Ruby: 200 MHz DECchip 21064 (EV4) processor(s).
The possible values of 'x' is 1 to 6. These numbers specify the number of microprocessors in the system.
[edit] Hardware description
The DEC 7000/10000 AXP are 6-way SMP capable systems based on nine nodes that are interconnected by the 128-bit LSB bus. The bus, which is pipelined, runs at 50 MHz and yields a maximum usable bandwidth of 640 MB/s. Eight of the nine nodes can be populated by a combination of CPU and memory modules, as long as the number of CPU modules is one to six, and one to seven for memory modules. The inclusion of a I/O module at node nine is mandatory and the slot for the module was physically incompatible with other modules to ensure this.
[edit] CPU module
Numerous CPU modules were available for these systems. The initial VAX 7000/10000 Model 600 used the KA7AA module, which featured a 90.9 MHz NVAX+ microprocessor, while later VAX-based systems such as the Model 700 and 800 used the KA7AB and KA7AC modules, which featured faster NVAX5 microprocessors. The Alpha-based DEC 7000/10000 Model 600 AXP used the KN7AA module which featured a 182 MHz DECchip 21064 microprocessor initially, which was later upgraded to 200 MHz. The Model 700 used the KN7AB module featuring 275 MHz DECchip 21064A. Other than the differences in microprocessor and clock frequencies, all CPU modules also featured 4 MB of Bcache (L2 cache) and two LEVI gate arrays for interfacing the module to the LSB bus. The CPU modules are interchangeable and Digital intended customers with the VAX-based systems to eventually upgrade to the Alpha by simply swapping them.
[edit] Memory module
The DEC 7000/10000 uses the MS7AA memory module with capacities of 64 MB, 128 MB, 256 MB, 512 MB, 1 GB and 2 GB. The module and its components are clocked at 50 MHz. The MIC (Memory Interface Controller), provides the interface to the LSB bus, and is comprised of two gate arrays, MIC-A and MIC-B. The two gate arrays both provide a 64-bit data path, which when combined results in a 128-bit data path that matches the width of the LSB bus. The two gate arrays, while similar, are not identical. MIC-A also serves as the memory controller, interfaces to the LSB bus' control lines and coordinates the operation of MIC-B, which provides the module with SECDED ECC capability.
Also on the module are 18 MDC (Memory Data Controller) chips. The purpose of the MDCs is to act as a buffer between the 512-bit memory bus and the 128-bit LSB bus. During memory read operations, the MDCs buffer a 512-bit transaction from the memory and forwards it to the MIC in four 128-bit transactions over four 20 nanosecond cycles. Memory write operations are similar, but with the roles reversed. The MDCs instead accumulate four 128-bit transactions from the MIC over four 20 nanosecond cycles before writing to the memory in one 512-bit transaction.
The memory is implemented with 4 or 16 MB DRAM chips and organised into one to eight 'strings', each consisting of 144 DRAM chips. Depending on the module's capacity, the DRAM chips are either surface mounted on both sides of the board or mounted on SIMMs that are soldered onto the board. The SIMMs are not socketed as Digital's engineers found the arrangement to be unreliable.
The modules and the memory subsystem of the DEC 7000/1000 supports interleaving. Modules with more than two strings supports two-way interleaving. At a system level, the memory subsystem supports a maximum of eight-way interleaving. If the configuration results in more levels of interleaving than the memory subsystem can support, multiple memory modules are then grouped into larger banks so the level of interleaving in the memory subsystem does not exceed the maximum of eight ways.
[edit] I/O module
The I/O module contains four parallel ports (not to be confused with these parallel ports) that connect to expansion drawers or cabinets via three meter cables. The expansion drawers or cabinets then implement different buses such the FutureBus+ Profile B and XMI expansion buses and SCSI and DSSI. Also on the I/O module is a I/O controller gate array, whose purpose is to interface the module to the LSB bus and to serve as a bridge, receiving a transaction from a bus and passing it on to another.
[edit] References
- AlphaServer comparison chart, March 1994 edition
- DEC 7000/10000 AXP KN7AA CPU Technical Manual, EK-KN7AA-TM.001, July 1993, Digital Equipment Corporation
- DEC 7000/10000 AXP, VAX 7000/10000 Platform Technical Manual, EK-7000A-TM.001, August 1993, Digital Equipment Corporation
- DEC 7000/10000 AXP, VAX 7000/10000 Systems Overview, EK–71XEA–OV.A01, First Printing, August 1993, Digital Equipment Corporation.
- MS7AA Memory Technical Manual, EK-MS7AA-TM.001, November 1992, Digital Equipment Corporation
- Paul Hardy's VMS CPU Model Summary
- Allison, Brian R. and van Ingen, Catharine, "Technical Description of the DEC 7000 and DEC 10000 AXP Family", Digital Technical Journal 4(4).
- VAX 7000/10000 KA7AA CPU Technical Manual, EK-KA7AA-TM.001, December 1992, Digital Equipment Corporation
|
||||||||||||||||||||||||||
